1. Field of the Invention
The present invention relates to a system, method, and program for controlling multiple storage devices.
2. Description of the Related Art
A local input/output (I/O) bus is a high-speed input/output (I/O) bus used for coupling peripheral devices, such as storage devices, to a computer system. The Peripheral Component Interconnect (PCI) bus and enhancements to the PCI bus, such as the PCI-X bus, are the commonly used I/O buses.
A PCI physical device is a physical device that may be coupled to the PCI bus. Each PCI physical device may incorporate from one to eight separate PCI functions. A PCI function may be a logical device. Each PCI function may include a configuration header that may be configured to control peripheral devices coupled to the PCI bus. The configuration header may include configuration registers, such as base address registers. Six base address registers comprising base address register 0 (BAR0), base address register 1 (BAR1), base address register 2 (BAR2), base address register 3 (BAR3), base address register 4 (BAR4), base address register 5 (BAR5) may be present in the configuration header. Each base address register may be 32 bits, i.e., a dword. Further details of the PCI bus (i.e., the PCI specification) are described in the publication entitled “PCI Local Bus Specification” by the PCI Special Interest Group (Revision 2.2, Copyright 1992, 1993, 1995, 1998 PCI Special Interest Group) and base address registers are described in Chapter 6 of the PCI specification.
A device adapter, such as a host bus adapter (HBA), may act as the interface between the PCI/PCI-X bus and the storage devices. The interface can control the transfer of data from a computer to a storage device and vice versa. Interfaces for storage disks include the Integrated Drive Electronics (IDE) interface (known also as an Advanced Technology Attachment interface, i.e., ATA, interface) and the Serial ATA (SATA) interface. Further details of SATA are described in the publication entitled “Serial ATA: High Speed Serialized AT attachment” by the Serial ATA Working Group (Revision 1.0, Copyright 2001). Technologies analogous to IDE/ATA such as the ATA packet interface (ATAPI) are available for CD ROM and DVD drives. The bandwidth and processing capabilities of the interface can substantially affect system performance, system configuration, system compatibility, system upgradability, etc.
A channel is typically the data pathway over which information flows in the IDE interface. As per the PCI IDE interface there may be two channels, primary channel and secondary channel, per PCI function. Furthermore, each channel can support at most two devices. For example, the primary channel can supports two IDE storage devices and the secondary channel can support two IDE storage devices. The configuration header of the PCI function may be configured to control four PCI IDE devices attached to the PCI bus. BAR0, BAR1, BAR2, BAR3 and BAR4 may be configured as I/O BARs. I/O BAR0 may be the command register block for the primary channel. I/O BAR1 may be the control register block for the primary channel. I/O BAR2 may be the command register block for the secondary channel. I/O BAR3 may be the control register block for the secondary channel. I/O BAR4 may provide control for bus master registers for both the primary channel and the secondary channel. BAR5 may be device specific, i.e., BAR5 is not part of the PCI IDE specification. Hence, a single PCI function can control at most four IDE storage devices via the two channels. Configuring the BARs as I/O BARs for PCI IDE is described in the publication entitled “PCI IDE Controller Specification” (Revision 1.0, 1994) in pages 1-5.
Although in the prior art PCI IDE/ATA has been used for supporting peripheral devices, there is a need in the art for improved techniques for controlling peripheral devices in a local I/O bus architecture with interfaces such as the SATA.